The present invention relates generally to analog-to-digital conversion, and more particularly, to an adaptive, analog-to-digital conversion using successive approximation.
Analog-to-digital converters (ADCs) are widely used in modern electronic equipment for converting analog signals to digital signals. A successive approximation algorithm is commonly used for the analog-to-digital conversion. Each analog-to-digital conversion cycle includes a sampling cycle for sampling the analog input signal to obtain a sampled voltage. The sampling cycle is followed by a comparison cycle in which the sampled voltage is compared with a series of comparison voltages generated based on a digital code. Each successive comparison voltage in the series is generated by setting the next most significant bit (MSB) of the digital code to binary 1 and the preceding bit to the original state, i.e., binary 0, resulting in each successive comparison voltage either being half of the preceding comparison voltage or being a sum of or difference between half of the preceding comparison voltage and half of a successive voltage range. If the sampled voltage is greater than a comparison voltage, the corresponding bit of the digital signal is set to binary 1, else the bit is set to binary 0. The above process is repeated for each bit of the digital signal, progressing from the MSB to the least significant bit (LSB).
Each comparison cycle includes multiple sub-comparison cycles corresponding to multiple bits of the digital signal. Therefore, the higher the resolution of the ADC, the higher the number of sub-comparison cycles and the longer the analog-to-digital conversion time. Thus, throughput of the ADC is reduced and power consumption is increased.
Therefore, it would be advantageous to have an ADC that has a reduced analog-to-digital conversion time, increased throughput, and reduced power consumption.